The present invention relates to formation of cobalt silicide on a silicon surface.
Cobalt silicide has been used to reduce the resistance of transistor gates and source/drain regions in silicon integrated circuits. Cobalt silicide can be formed in a self-aligned manner by a “salicide” (self-aligned silicide) process illustrated in FIGS. 1 and 2. These figures show a polysilicon gate 100 and source/drain regions 101 of a MOS transistor fabricated in a wafer 102. The source/drain regions 101 are doped regions of a monocrystalline silicon substrate 104. Gate dielectric 108 separates the gate 100 from the substrate. Dielectric spacers 110 cover the sidewalls of gate 100.
A cobalt layer 120 is sputtered over the structure. A titanium layer 130 is sputtered on cobalt 120 to protect the cobalt layer from oxygen and other impurities during subsequent processing. Then the wafer is heated (in a rapid thermal processing step, or RTP) to react cobalt 120 with the silicon at the top of gate 100 and on source/drain regions 101. A cobalt silicide layer 210 (FIG. 2) forms as a result. This layer may include cobalt monosilicide CoSi and cobalt disilicide CoSi2. Titanium 130 and the unreacted cobalt are removed with a wet etch. The wafer is heated again to increase the proportion of cobalt disilicide CoSi2 in layer 210 and thus reduce the layer 210 resistivity. See H. Li et al., “Gaseous Impurities in Co Silicidation”, Journal of The Electrochemical Society, 148 (6) G344–G354 (2001), incorporated herein by reference.
In addition to protecting the cobalt layer 120 from impurities, some of titanium 130 may diffuse to the cobalt/silicon interface and dissolve the native silicon oxide, thus allowing the cobalt silicide to form (the cobalt itself does not dissolve the native oxide).
The cobalt salicide process has been suggested for silicidation of silicon surfaces at the bottom of openings formed in dielectric layers deposited over silicon. When cobalt 120 is deposited in the openings, a good step coverage is needed in order to have a sufficient cobalt thickness at the bottom of the openings and thus achieve low cobalt silicide resistivity. As the integrated circuit technology is scaled down to smaller line widths, the aspect ratios of the openings tend to increase, and achieving a good step coverage of the cobalt film becomes increasingly difficult. Applied Materials, Inc. has announced that its Endura® ALPS™ (Advanced Low Pressure Source) cobalt deposition chamber can provide greater than 10% bottom coverage in 6:1 aspect ratio contact openings. Further improvements in the cobalt silicide fabrication are desirable.